Rashmi Jha

Rashmi Jha

Rashmi Jha, PhD

Biography

Rashmi Jha holds a PhD in Electrical Engineering from North Carolina State University (2006) and a Master of Science in Electrical Engineering also from North Carolina State University (2003). Prior to that she attended Indian Institute of Technology (IIT), where in 2000 she earned her Bachelor of Science in Electrical Engineering. The recipient of multiple research grants, Jha has served as the director at the Microfabrication Laboratory and the Nanoelectronic Materials and Devices Laboratory both at University of Toledo.

Jha serves on multiple boards, peer review panels, professional committees, and participates in outreach activities for broadening participation of underrepresented groups in science and engineering and service to the broader community. She is actively engaged in the entrepreneurship community where she has served in the panel for technology evaluation at the University of Toledo Innovation Enterprises, has coined a pre-startup company named Y-Scales that is evaluating the commercialization prospects of ReRAM devices, and has developed proposals to secure funding from Ohio Third Frontier opportunities for technology evaluation of ReRAM devices.

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Research Interests

  • Nanoelectronic Devices Enabled Future Neuromorphic Computing Systems
  • Resistive Random Access Memory Devices
  • Spintronics
  • Neuroscience and Cognitive Modeling
  • Neuroelectronics, Emerging Nanoscale Devices Enabled Cyber-Security Systems
  • Invisible Logic and Memory Devices for Wearable Computing
  • Solid Oxide Battery Devices
  • Energy Harvesting Devices

Professional Experience

University of Cincinnati, Cincinnati, OH
Associate Professor, Department of Electrical Engineering and Computing Systems
June 2015- Present
University of Toledo, Toledo, OH
Associate Professor, Department of Electrical Engineering and Computer Science
August 2014- May 2014
University of Toledo, Toledo, OH
Assistant Professor, Department of Electrical Engineering and Computer Science
April 2008-July 2014
IBM, East Fishkill, NY
Process Integration Engineer, Semiconductor Research and Development Center
August 2006- March 2008
North Carolina State University, Raleigh, NC
Graduate Research Assistant
August 2002- August 2006
Geometric Software Solutions System, India
Software Engineer
August 2000-July 2002

 

Honors and Awards

CAREER Award, National Science Foundation 2013
Researcher of the Year Award, EECS Dept. University of Toledo 2013
Summer Faculty Fellowship Award, National Nanotechnology Infrastructure Network (NNIN) 2013
IBM Faculty Award, IBM Corporation 2012
Invention Achievement Award, IBM Corporation 2007
Graduate Student Award, Materials Research Society (MRS) 2006
Best Student Paper Award Nomination, IEEE/ IEDM 2005
Graduate Fellowship Award, Applied Materials Inc. 2005-2006
Graduate Research Assistantship Award, North Carolina State University 2002-2005

 

Patents

  1. Nanoelectronic Memristor Devices with Dilute Magnetic Semiconductors, U.S. Pat. No., 8,502,343 B1 issued in August 6, 2013.
  2. PFET with Tailored Dielectric and Related Methods and Integrated Circuit, US 8053306 B2, 11-08-issued in 2011.
  3. Structure and Method to Control Oxidation in High-K Gate Structures, US 7955926 B2, 06-07-2011.
  4. Gate Effective Workfunction Modification for CMOS, US 7947549 B2, 05-24-2011.
  5. Dual Metal And Dual Dielectric Integration for Metal High-K FETs, US 7943457 B2, 05-17-2011.
  6. Methods for Forming Dual High-K Metal Gate Using Photoresist Mask and Structures Thereof, US 7915115 B2, 03-29-2011.
  7. Method and Structure for Threshold Voltage Control and Drive Current Improvement for High-K Metal Gate Transistors, US 20100244206 A1, 09-30-2010.
  8. Semiconductor Device Having Dual Metal Gates and Methods To Manufacture, US 20100187610 A1, 07-29-2010.
  9. Changing Effective Workfunction Using Ion Implantation During Dual Workfunction Metal Gate Integration, US 20100038725 A1, 02-18-2010.
  10. In-Situ Silicon Cap for Metal Gate Electrode, US 20090308636 A1, 12-17-2009.
  11. Gate Stack Structure with Oxygen Gettering Layer, US 20090152651 A1, 06-18-2009.
  12. Dielectric Spacer Removal, US 20090065817 A1, 03-12-2009.

Selected Journal Publications

  1. Saptarshi Mandal, Ammaarah El-Amin, Kaitlyn Alexander, Bipin Rajendran, and Rashmi Jha, “Novel Synaptic Memory Device for Neuromorphic Computing”, Nature Scientific Reports, Vol.4, Article No. 5333, June 2014.
  2. S. Mandal, B.Long, R.Jha, “Study of Synaptic Behavior in Doped Transition Metal Oxide-Based Reconfigurable Devices”, IEEE Transactions on Electron Devices, Vol. 60, Iss. 12, 2013.
  3. Branden Long, Saptarshi Mandal, Joseph Livecchi, and Rashmi Jha, “Effects of Mg-Doping on HfO2 Based ReRAM Device Switching Characteristics”, IEEE Electron Device Letters, Vol.34, Iss.10, Oct. 2013.
  4. Branden Long, Yibo Li, Saptarshi Mandal, Rashmi Jha, and Kevin Leedy, “Switching Dynamics and Charge Transport Studies of Resistive Random Access Memory Devices”, Applied Physics Letters, Vol. 101, 113503, 2012.
  5. Branden Long, Yibo Li, Rashmi Jha, “Switching Characteristics of Ru/HfO2/TiO2-x/Ru RRAM Devices for Digital and Analog Non-Volatile Memory Applications”, IEEE Electron Device Letters, Vol. 33, No.5, May 2012.
  6. Branden Long, Jorhan Ordosgoitti, Rashmi Jha, Christopher Melkonian, “Understanding the Charge Transport Mechanism in Transition Metal Oxide Based Nanoelectronic Memristor Devices”, IEEE Transactions on Electron Devices, Vol. 58, Issue 11, Nov. 2011.
  7. M. Chowdhury, B. Long, R. Jha, V. Devabhaktuni, “A fundamental understanding of Nickel Oxide based Resistive Random Access Memory with High Percentage of Oxygen”, Elsevier Solid State Electronics, Vol. 68, pp 1-3, Feb. 2012.
  8. Madhumita Chowdhury, Branden Long, Rashmi Jha, Vijay Devabhaktuni, “Charge ConductionMechanism and Modeling in High-K Dielectric Based MOS Capacitor”, International Journal of Modern Engineering, Vol. 12, Iss. 1, 2011.
  9. B.Chen, R.Jha, V.Misra, “Work Function Tuning Via Ultra Thin Charged Reaction Layers Using AlTa and AlTaN Alloys”, IEEE, Electron Device Letters, Vol. 27, Iss.9, Sept. 2006.
  10. D. J. Lichtenwalner, J.S. Jur, R. Jha, N. Inoue, B. Chen, V. Misra, A.I. Kingon, “High-temperature stability of lanthanum silicate gate dielectric MIS devices with Ta and TaN electrodes”, Journal of the Electrochemical Society, 153 (9), F210-F214 2006.
  11. B. Chen, R. Jha, H. Lazar, N. Biswas, J. Lee B. Lee, L. Wielunski, E. Garfunkel, V. Misra, “Influence of oxygen diffusion through capping layers of low work function metal gate electrodes”, IEEE, Electron Device Letters, Vol. 27, Iss.4, Apr. 2006.
  12. R. Jha, J.H.Lee, P. Majhi, V. Misra, “Investigation of Work Function Tuning using Multiple Layer Metal Gate Electrodes Stacks for Complementary Metal Oxide Semiconductor Applications”, Applied Physics Letters, Vol.87, 223503, 2005.
  13. R. Jha, J. Gurganus, Y.H. Kim, R. Choi, J. Lee, V. Misra "A Capacitance-Based Methodology for Work Function Extraction of Metals on High-k”, IEEE Electron Device Letters, Vol. 25 , Issue 6, Pages: 420 – 423, June 2004.

Selected Technical Presentations

  1. “Nanoelectronic synaptic devices and materials for brain-inspired computational architectures”, (Invited Talk) Rashmi Jha, SPIE Conference, San Diego, CA, Aug. 2014.
  2. “Analog and Digital Switching Characteristics of Transition Metal Oxide Based Resistive Random Access Memory Devices”, (Invited Talk), IEEE International Semiconductor Devices Research Symposium (ISDRS), Maryland, Dec 2013.
  3. “Temperature Dependent Studies to Understand the Mechanism of Switching in Resistive Random Access Memory Devices”, (Invited Talk), 224th ECS Meeting, San Francisco, 2013.
  4. “Resistive Random Access Memory Devices: Opportunities and Challenges”, T.J. Watson Research Center, IBM, July 2013.
  5. “Understanding the Role of Dopants in Transition Metal Oxide Dielectrics for Digital and Analog Resistive Switching”, (Invited Talk), 223rd ECS Meeting, Toronto, CA, May 2013.
  6. “Mechanism of Switching and Related Challenges in Transition Metal Oxide Based RRAM Devices”, Flash Memory Summit, Santa Clara, CA, Aug 20-24, 2012.
  7. “Understanding the Switching Mechanism in Transition Metal Oxide Based ReRAM Devices”, IEEE ISVLSI Conference, University of Massachusetts, Amherst, MA, Aug 20-22, 2012.
  8. “Understanding the Role of Electrodes in Doped Transition Metal Oxide Based Nanoelectronic Memristor Devices”, MRS Spring Meeting, San Francisco, April 2011.
  9. “Nanoelectronic Memristor Devices for the Next Generation of Memory and Logic Applications”, Invited Talk, University of Cincinnati, Cincinnati, Ohio, November 2010.
  10. “High-K Metal Gates Based Next Generation CMOS Devices”, Seminar, University of Michigan, Ann Arbor, Michigan, April 2010.
  11. “High-K Technical Vitality”, Technical Seminar, IBM, East Fishkill, NY 12553, Apr. 2007.
  12. “Role of Interfaces in Determining the Effective Work functions of Metals on High-K Dielectrics”, SRC/SEMATECH FEP Transition Center Review, North Carolina State University, Raleigh, NC , Nov. 2005.
  13. “Modulation of the Interface in Determining the Effective Work Function of Metal Gates on High-K Gate Dielectrics”, FEP Gate Stack Engineering Working Group Meeting, Sematech, Austin, TX, Feb. 2005.
  14. “Work Function Extraction of Metal Gates on High-k Gate Dielectrics”, SRC/SEMATECH FEP Transition Center Review, North Carolina State University, Raleigh, NC, Nov. 2004.