Rapid Certification Program Curriculum
OASIS is offering short courses focused upon the needs of the semi-conductor industry. Approximately 8 weeks long, these interactive courses will prioritize hands-on experience.
Certification Levels
Whether you're entirely new to the field of semiconductors or seeking to broaden your already in-depth experience, OASiS has micro-credit course options tailored to your needs.
- Co-taught with community college and regional UC campus faculty
- Skills developed: Cleanroom safety, protocols, and professional skills
- Virtual lectures and in-class projects
- Skills developed: Fundamentals of semiconductor fabrication and manufacturing skills
- Simulation/VR experience and class lecture
- Skills developed: Intermediate semiconductor fabrication and manufacturing skills, metrology, experimental design, and critical thinking
- In-depth lab experience and extensive hands-on cleanroom experience
- Skills developed: Advanced device fabrication design
Program Curriculum & Courses
Throughout each program, there are general education courses and different levels to choose from and upskill in each area. From safety to process technology, OASiS offers courses in innovative fields. There are different levels to choose from and upskill in each area:
- Intro to Semiconductor Devices
- Intro to Cleanroom and Safety Protocols
- Chemicals in Semiconductor Fabrication
- IC Fabrication Process Workflow
- Fundamentals of Device Fabrication
- Silicon and Wafer Prep
- Introduction to Manufacturing and Equipment Safety
- Semiconductor Professional Skills Course
Rapid Certification Program courses will cover very preliminary material with the goal of teaching cleanroom, gowning and safety protocols; basic handling of silicon wafers, silicon wafer cleaning, as well as professional skills specific to the semiconductor industry, including how to craft a relevant resume.
Level 1: Rapid certification curriculum
Module Name/Course |
Topics |
Intel’s Training Needs |
Introduction to Silicon (UD EGR 2XX)*New |
Intro to Si, structure, properties, crystal growth, doping, wafer- processing, cleanroom intro |
Silicon and wafer prep, chemicals in semiconductor fab
|
Semiconductor Fabrication Processes (UD EGR 311) |
Oxidation, diffusion, photolithography, lift-off metallization, etching, etc. |
IC fabrication process workflows |
Introduction to Thin Films (UD EGR 2XX)*New |
Intro to electronic, dielectric, optical and magnetic thin films |
Fundamentals of device fab, transistor technology |
Level 2: Foundation curriculum
| Module Name/Course |
Topics |
Intel’s Training Needs |
Thin Film Deposition Systems (UD EGR 311) |
Vacuum systems, mass flow controller, pressure gauges, leak detection, power supplies (DC & RF), power supply tuning |
Fundamentals of device fabrication |
Thin Film Processing (UD EGR 311) |
CVD, Sputtering, e-beam evaporation, thermal evaporation, pulsed laser deposition, MBE, MOCVD, ALD |
Fundamentals of device fabrication |
Level 3: Intermediate curriculum
Module Name / Course |
Topics |
Intel’s Training Needs |
Thin Film Characterization (UD EGR 4xx)*New |
SEM, XRD, Ellipsometry, XPS, AFM, TEM, etc. |
Semiconductor metrology |
Level 1: Rapid certification curriculum
Module Name/Course |
Topics |
Intel’s Training Needs |
Introduction to CMOS Devices, Scaling and Moore’s Law (UC ECE 2XX) UC Delivery*: Lec (1.5hr) UC Cleanroom (1.5hr) |
Intro to semiconductor devices, p-n junctions, metal-semiconductor contacts, MOSFETs, CMOS devices, FEOL, MEOL, BEOL, packaging, roadmap |
Electrical engineering, device physics, process and device engineer and technicians |
CMOS Process Technology-I (UC ECE 2XX) UC Delivery*: Lec (1hr) UC Cleanroom (2hrs) UC-Advanced Materials Characterization Center (AMCC) (2hr)
|
Intro to cleanroom, gowning in bunny suits and safety protocols, basic handling of silicon wafer out of box, identification of n- and p-type, sheet resistance measurement using 4-point probes, doping, silicon wafer cleaning, front-end-of-line (FEOL) modules, inspection in scanning electron microscopy (SEM) |
Process integration, process engineer, equipment and manufacturing technicians, metrology engineer and technicians |
Semiconductor Equipment and Process (UC MME xx) UC Training in VR Lab |
Basic thin film physical vapor deposition system parts and operation |
Process engineer, equipment and manufacturing technicians |
Level 2: Foundation curriculum
Module Name / Course |
Topics |
Intel’s Training Needs |
CMOS Process Technology-II (UC ECE XX) UC Delivery*: Lec. (1hr) UC-Cleanroom (3hrs)
|
Thermal oxidation, ellipsometry for thickness measurement, data-analysis and statistical process control chart, lithography (mask design, photoresist, expose, develop), RIE, RF magnetron sputtering, FEOL, etc. |
Process integration engineer, process engineer, equipment technicians, manufacturing technicians |
Wafer Testing and Data Analysis (UC ECE XX) UC Delivery*: Lec (1hr) UC-Cleanroom (2hr) UC-AMCC (2hr) |
In-line parametric test, wafer sort, yield, wafer sort yield model, accelerated lifetime tests
|
Yield engineer, device engineer, wafer characterization technicians |
Semiconductor Equipment and Process (UC MME XX) UC Training in VR Lab |
Basic ALD system parts and operation |
Process engineer, equipment and manufacturing technicians |
IC Packaging and Full-System Characterization Lec (2hr) CAD/EDA Lab (2hr) |
Signal and power integrity in on-and off-chip high-speed signal propagation scenarios, packaging solutions’ electrical performance assessment, S-parameter analysis of multi-port interconnect, interconnect modeling using CAD/EDA (e.g., Ansys HFSS®) |
Electrical engineering, circuit and layout design, process engineer, system engineer |
Level 3: Intermediate curriculum
Module Name/Course |
Topics |
Intel’s Training Needs |
CMOS Process Technology-III (UC ECE XX) UC Delivery*: Lec. (1hr) UC-Cleanroom (2hr) UC-Advanced Materials Characterization Center (2hr)
|
Atomic layer deposition (ALD), low-temperature oxidation, nitrides, silicidation process, MEOL, BEOL, metrology and microscopy (SEM, XRD, Raman), interfaces and contamination (XPS), line edge roughness, defect/fault analysis using SEM |
Process integration, process engineer, yield engineer, equipment technicians, manufacturing technicians |
Digital IC Design and PDKs UC (UC ECE XX) (UD ECE 441/530) Delivery*: Lec. (1hr) Simulation Lab (2hr) |
VLSI, pre- and post-silicon validation, layout, PDKs |
Circuit and layout design and fabrication |
CMOS Analog Circuit Design Lec (2hr) Lab (2hr) |
CMOS physics, CMOS layout fundamentals, analog front-end (AFE) CMOS circuit design, system integration, post-silicon validation of analog interfaces (e.g., using nanoprobing) |
Electrical engineering, circuit and layout design, device physics, process engineer |
Silicon Photonic Devices and Circuits (UD ECE 402*(new)/EOP 605) |
Photonics IC design, AIM photonics PDK |
Silicon based photonics technology |
Optical Interferometry and Metrology (UD EOP 603) |
Interference, diffraction and holography, classical interferometers, fringe analysis, holographic, phase-shifting, white-light and speckle interferometry, fiber-optic interferometers and gyros, applications in nondestructive testing, LiDAR, bio-sensing and imaging, semiconductor processing |
Semiconductor metrology |
EO Crystal Growth and Applications (UD EOP 595) |
Review of crystal growth techniques and underlying mechanisms with relevant theory, selection of crystal materials and their importance, introduction to processes for crystal fabrication and characterization, prototype crystal components, applications of crystals in selected electro-optical systems |
Crystal growth fundamentals and lab experiences |
Level 1: Rapid certification curriculum
Module Name/Course |
Topics |
Intel’s Training Needs |
Automation and Computer Vision Fundamentals (Online): Lec (1hr) Self-guided Lab (2hr) |
Intro to automation via hands-on online instruction focusing on building autonomous robots with computer vision capability |
Electrical engineering, process and device engineer and technicians |
Introduction to Facilities Design (UD IET 332) WSU |
Intro to facility layout design process, product, process and schedule design, flow-systems, space requirements and activity relationships, personnel requirement, layout design algorithms, layout planning models, material handling |
Manufacturing, assembling and packaging facility design |
Process Capability and Analysis (UD IET 318) |
Basic statistics, variable control charts, process capability, other variable control charts, probability |
Fundamentals of manufacturing/production process capability
|
Fundamentals of Industrial Engineering (WSU New) |
Introduction to machines, manufacturing, safety |
Fundamentals of manufacturing |
Six Sigma – 1 (WSU) |
Voice of the customer, data driven management, process behavior and charting |
Quality |
Introduction to semiconductor manufacturing (WSU New) |
Intro to cleanroom operation, safety regulations, material handling, intro to device types, intro manufacturing processes (FEOL and packaging (BEOL) |
Fundamentals of manufacturing
|
Level 2: Foundation curriculum
Module Name/Course |
Topics |
Intel’s Training Needs |
Process Control and Automation (Online) Lec (1hr) Self-guided Lab (2hr) WSU |
First principle models and process dynamics, PID controllers, HMI, historian, DCS, and SCADA, PLC programming, big data analysis and statistical process control, advanced control methods, auxiliary systems, AI and Industry 4.0 |
Process engineering, yield engineer, equipment and manufacturing technicians |
Facility Design II (UD IET 332) Industrial: Factory Floor Planning (WSU) |
Warehouse operations, manufacturing systems, facilities systems, quantitative models for facility planning |
Semiconductor manufacturing and storage layout design
|
Six Sigma – 2 (WSU) |
Project selection, DMAIC framework |
Quality |
Lean - 1 (WSU) |
Lean manufacturing concept, value stream mapping, Just-in-time production, Kanban |
Production planning, scheduling and control (WIP management) |
Statistical Process Control (WSU New) |
DoE, fundamentals of statistics in manufacturing, JMP, project management |
Quality |
Level 3: Intermediate curriculum
Module Name/Course |
Topics |
Intel’s Training Needs |
Circuit Design and Statistical Analysis for HVM Lec (3hr)
|
CMOS analog and digital circuit design case studies, statistical analysis of design outcome variations, parametric modeling, response surface methodology (RSM) |
Electrical engineering, process integration, process engineer, yield engineer, circuit and layout design |
Facility Design III (UD IET 332) |
evaluating layout efficiency, selecting and implementing the optimum layout, maintaining facility layout
|
Efficient semiconductor processing facilities |
Production Planning and Process Control (UD IET 318) WSU |
aggregate planning, quality control charts for attributes, reliability, advanced topics in quality, quality costs, product liability, benchmarking and auditing |
Production planning and process control |
Metrology for Manufacturing Quality Assurance |
Quality analysis and understanding data. |
Manufacturing, assembling and packaging facility design |
Six Sigma -3 (WSU) |
Six sigma culture, Class project – Green belt certification after the completion of all 3 levels |
Quality |
Lean – 2 (WSU) |
Kaizen, Poke-yoke, Small lot production, SMED, Performance measures |
Production planning, scheduling and control (WIP management) |
Product Engineering (WSU New) |
Product engineering, JMP, failure analysis, FMEA, New product initialization, process validation and documentation |
Manufacturing, Quality |
Note: HMI = human-machine interfaces, SCADA = systems control and data acquisition, Historian= responsible for logging and storing all data from SCADA, DSC = digital security controls
Level 1: Rapid certification curriculum
Module Name/Course |
Topics |
Intel’s Training Needs |
Industrial Environmental Control Lec (3hr) |
Water and air pollution and control technologies, computer-based modeling applications, selection between alternative pollution control strategies, environmental regulations, technical, economical and ethical aspects of environmental engineering |
Process engineer, environmental engineer, sustainability officer |
Seeing Differently (Virtual sessions 8 weeks + 1 in person session) |
A new non-traditional and advanced transformational leadership program in which cohorts of people from different backgrounds (students, professionals, etc.) participate |
Leadership, organization and communication skill, social perceptiveness |
Chemical Waste in Semiconductor Industry (UD EGR 2XX)*New |
Intro to hazardous materials and their classification, history and usage, toxicity and health effects
|
Regulatory difference between waste categories, health and safety issues
|
Chemical Safety Protocols (UC Chem/Env) UC |
N/A |
N/A |
Ethics in Semiconductor, Diversity and Inclusion UC (UC XX) (Whitney & PK) |
N/A |
N/A |
Level 2: Foundation curriculum
Module Name/Course |
Topics |
Intel’s Training Needs |
Seeing Differently (Virtual sessions 8 weeks + 1 in person session) |
A new non-traditional and advanced transformational leadership program in which cohorts of people from different backgrounds (students, professionals, etc.) participate |
Leadership, organization and communication skill, social perceptiveness |
Chemical Waste Characterization (UD EGR2XX)*New |
Source identification, sampling approaches, analytical methods, qualitative analysis, risk assessment and compliance |
Environmental health and impact assessment |
UC Course: (Open Slot) UC |
N/A |
N/A |
Level 3: Intermediate curriculum
Module Name/Course |
Topics |
Intel’s Training Needs |
Seeing Differently (Virtual sessions 8 weeks + 1 in person session) |
A new non-traditional and advanced transformational leadership program in which cohorts of people from different backgrounds (students, professionals, etc.) participate
|
Leadership, organization and communication skill, social perceptiveness |
Semiconductor Waste Remediation (UD EGR3XX)*New |
Waste reduction, elimination and treatment |
Sustainability best practices, environmental safety, emerging treatments for waste |
UC Course (open slot) UC |
N/A |
N/A |
