Microelectronics and Integrated-Computing-Systems with Nanoelectronic Devices (MIND) Lab

Project 1: Advanced Semiconductor Logic and Memory Devices:

: Moore’s law of CMOS transistor scaling has been the backbone of microelectronics and digital computing revolution so far1. However, transistor gate lengths have already reached to around 2 nm (i.e. Angstrom Era) and it is increasingly difficult to scale down the size of transistors due to limitations imposed by the device physics2. On the other hand, computing and data storage needs have increased drastically. It is well-recognized that novel device technologies for logic computing and data storage is necessary to address the demands of future computing. Students working on this project will work on advanced logic and memory device technology with a blend of both hands-on research in CEAS Cleanroom and MIND lab, and modeling. Ideal candidate will be EE student with interest in pursuing career in Semiconductor fabrication industry such as Intel or research in this area.     

Project 2: Neuromorphic Computing Architecture with Emerging Neuronal and Synaptic Memory Devices

This project will involve Device Technology Co-optimization (DTCO) and System Technology Co-optimization (STCO) approaches for low-power computing architectures to enable Edge AI3. Students will research on various neuromorphic computing architectures and how they compare to the cortical circuitries in brain and designing brain-inspired architectures for cognitive data analytics in edge applications, such as sensors and transceivers. Ideal candidate will be CPE student with interest in pursuing career in Semiconductors and other Fabless Microelectronics design companies such as Intel, Google, Qualcomm, Nvidia.      

References: 

1. https://www.intel.com/content/www/us/en/silicon-innovations/moores-law-technology.html

2. K. J. Kuhn, "Moore's Law Past 32nm: Future Challenges in Device Scaling," 2009 13th International Workshop on Computational Electronics, 2009, pp. 1-6, doi: 10.1109/IWCE.2009.5091124. 

3. A. Mallik et al., "Design-technology co-optimization for OxRRAM-based synaptic processing unit," 2017 Symposium on VLSI Technology, 2017, pp. T178-T179, doi: 10.23919/VLSIT.2017.7998166.

About the MIND Lab

MIND lab (located in Rhodes Hall 937) is engaged in interdisciplinary research in the areas of advanced semiconductor logic and memory device design, fabrication, testing, and modeling. Our research also involves developing novel computing circuitries and architectures, such as brain-inspired computing architectures, hardware accelerator for AI, neuromorphic architectures and synaptic memory devices, and cross-technology heterogenous/monolithic integration. We also explore approaches for developing secure microelectronics hardware and assurance techniques by integrating novel device technologies in CMOS Platforms. MIND lab has graduated many PhD, MS, and UG students in research who are now placed in reputed companies such as Intel, Micron, Apple, Google, Microsoft, and Riverside Research. Students performing research in MIND lab have published their work in highly reputed journals, attended conferences, and filed/granted patents. Additionally, two Protégé students from MIND lab  have been the recipients of second place in past Protégé research symposiums. 

Director

Headshot of Rashmi Jha

Rashmi Jha

Professor, CEAS - Electrical and Computer Engineeri

385 MANTEI

513-556-1361

Dr. Rashmi Jha is Professor in Electrical Engineering and Computer Science Department at the University of Cincinnati. She was an Associate Professor at the University of Cincinnati from 2015-2020. She worked as an Assistant Professor and then Associate Professor in Electrical Engineering and Computer Science Department at the University of Toledo from 2008 to 2015. Before this, she worked as a Process Integration Engineer for 45 nm/32 nm High-k/Metal Gates based Advanced CMOS technology at Semiconductor Research and Development Center, IBM, East Fishkill New York between 2006-2008. She finished her Ph.D. and M.S. in Electrical Engineering from North Carolina State University in 2006 and 2003, respectively, and B.Tech. in Electrical Engineering from Indian Institute of Technology (IIT) Kharagpur, India in 2000. She has more than 18 years of experience in the areas of Solid State Electronics and Nanoelectronic Device Design, Modeling, Fabrication, Process Integration, Electrical Characterization, Data Analysis, Circuit Design and Simulations.  She has been granted 13 US patents and has authored/co-authored several publications in the areas of computing devices, circuits, and algorithms. She has been a recipient of AFOSR Summer Faculty Fellowship Award in 2017, CAREER Award from the National Science Foundation in 2013, IBM Faculty Award in 2012, IBM Invention Achievement Award in 2007, Materials Research Society's Graduate Student Award in 2006, Applied Materials Fellowship Award in 2005-2006, and the best student paper award nomination in IEEE International Electron Devices Meeting (IEDM) in 2005. Her current research interests span all the way from devices to systems and algorithms. Particularly, she is interested in Artificial Intelligence (AI), Low-Power Neuromorphic Systems, CMOS and other emerging logic and memory devices ( such as Resistive Random Access Memory Devices, Spintronics, and other memristive devices), On-die sensors, Cross-Technology Heterogenous Integration and Modeling, Cybersecurity with emphasis on Hardware Security, Additive, Flexible, and Wearable Electronics, Nanoelectronics, Neuroscience and Neuroelectronics, Bio-Inspired Computing and Systems.
 
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